Here, the state control unit is composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units is connected to processor elements according to the plurality of element areas, each of the plurality of state control units being arranged in a respective element area of the plurality of element areas.
As a result, the plurality of state control units can independent control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition. Further, the state control units are connected to the plurality of processor elements in groups of each of the plurality of element areas, and the plurality of state control units are each directly connected to the processor elements for which they control states by the shortest possible distance. This construction enables a simplification of the wiring configuration of the array-type processor as well as an improvement in the productivity and operating speed of the array-type processor.
Still further, in the above-described array-type processor, buffer regions can be formed between adjacent element areas, transfer moderation circuits for moderating the data transfer of the processor elements of the element areas on both sides of the buffer regions can be arranged in the buffer regions, and common resources that are shared by the processor elements of element areas on both sides of the buffer regions can be arranged in the buffer regions.
The resulting moderation of data transfer of processor elements of element areas on both sides of a buffer region that is realized by the transfer moderation circuits allows the execution of data transfer without obstacles even when, for example, the processor elements of element areas on both sides of a buffer region operate at different clock cycles.
In addition, the sharing of common resources by processor elements of element areas on both sides of a buffer region enables, for example, hardware that is not provided for each and every one of the plurality of element areas to be used as a common resource by processor elements of element areas on both sides.
In the present invention, ‘plurality’ means any integer equal to or greater than 2, and ‘multiplicity’ means any integer that is greater than the above-described ‘plurality’.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention.